-- Copyright (C) 2018  Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
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-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors.  Please
-- refer to the applicable agreement for further details.

-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "10/20/2021 14:55:34"
                                                            
-- Vhdl Test Bench template for design  :  TrafficLight
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY TrafficLight_vhd_tst IS
END TrafficLight_vhd_tst;
ARCHITECTURE TrafficLight_arch OF TrafficLight_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL i_sys_clk : STD_LOGIC;
SIGNAL i_sys_emergency : STD_LOGIC;
SIGNAL i_sys_rst : STD_LOGIC;
SIGNAL o_ew_green : STD_LOGIC;
SIGNAL o_ew_red : STD_LOGIC;
SIGNAL o_ew_tens_a : STD_LOGIC;
SIGNAL o_ew_tens_b : STD_LOGIC;
SIGNAL o_ew_tens_c : STD_LOGIC;
SIGNAL o_ew_tens_d : STD_LOGIC;
SIGNAL o_ew_tens_e : STD_LOGIC;
SIGNAL o_ew_tens_f : STD_LOGIC;
SIGNAL o_ew_tens_g : STD_LOGIC;
SIGNAL o_ew_units_a : STD_LOGIC;
SIGNAL o_ew_units_b : STD_LOGIC;
SIGNAL o_ew_units_c : STD_LOGIC;
SIGNAL o_ew_units_d : STD_LOGIC;
SIGNAL o_ew_units_e : STD_LOGIC;
SIGNAL o_ew_units_f : STD_LOGIC;
SIGNAL o_ew_units_g : STD_LOGIC;
SIGNAL o_ew_yellow : STD_LOGIC;
SIGNAL o_ns_green : STD_LOGIC;
SIGNAL o_ns_red : STD_LOGIC;
SIGNAL o_ns_tens_a : STD_LOGIC;
SIGNAL o_ns_tens_b : STD_LOGIC;
SIGNAL o_ns_tens_c : STD_LOGIC;
SIGNAL o_ns_tens_d : STD_LOGIC;
SIGNAL o_ns_tens_e : STD_LOGIC;
SIGNAL o_ns_tens_f : STD_LOGIC;
SIGNAL o_ns_tens_g : STD_LOGIC;
SIGNAL o_ns_units_a : STD_LOGIC;
SIGNAL o_ns_units_b : STD_LOGIC;
SIGNAL o_ns_units_c : STD_LOGIC;
SIGNAL o_ns_units_d : STD_LOGIC;
SIGNAL o_ns_units_e : STD_LOGIC;
SIGNAL o_ns_units_f : STD_LOGIC;
SIGNAL o_ns_units_g : STD_LOGIC;
SIGNAL o_ns_yellow : STD_LOGIC;
COMPONENT TrafficLight
	PORT (
	i_sys_clk : IN STD_LOGIC;
	i_sys_emergency : IN STD_LOGIC;
	i_sys_rst : IN STD_LOGIC;
	o_ew_green : BUFFER STD_LOGIC;
	o_ew_red : BUFFER STD_LOGIC;
	o_ew_tens_a : BUFFER STD_LOGIC;
	o_ew_tens_b : BUFFER STD_LOGIC;
	o_ew_tens_c : BUFFER STD_LOGIC;
	o_ew_tens_d : BUFFER STD_LOGIC;
	o_ew_tens_e : BUFFER STD_LOGIC;
	o_ew_tens_f : BUFFER STD_LOGIC;
	o_ew_tens_g : BUFFER STD_LOGIC;
	o_ew_units_a : BUFFER STD_LOGIC;
	o_ew_units_b : BUFFER STD_LOGIC;
	o_ew_units_c : BUFFER STD_LOGIC;
	o_ew_units_d : BUFFER STD_LOGIC;
	o_ew_units_e : BUFFER STD_LOGIC;
	o_ew_units_f : BUFFER STD_LOGIC;
	o_ew_units_g : BUFFER STD_LOGIC;
	o_ew_yellow : BUFFER STD_LOGIC;
	o_ns_green : BUFFER STD_LOGIC;
	o_ns_red : BUFFER STD_LOGIC;
	o_ns_tens_a : BUFFER STD_LOGIC;
	o_ns_tens_b : BUFFER STD_LOGIC;
	o_ns_tens_c : BUFFER STD_LOGIC;
	o_ns_tens_d : BUFFER STD_LOGIC;
	o_ns_tens_e : BUFFER STD_LOGIC;
	o_ns_tens_f : BUFFER STD_LOGIC;
	o_ns_tens_g : BUFFER STD_LOGIC;
	o_ns_units_a : BUFFER STD_LOGIC;
	o_ns_units_b : BUFFER STD_LOGIC;
	o_ns_units_c : BUFFER STD_LOGIC;
	o_ns_units_d : BUFFER STD_LOGIC;
	o_ns_units_e : BUFFER STD_LOGIC;
	o_ns_units_f : BUFFER STD_LOGIC;
	o_ns_units_g : BUFFER STD_LOGIC;
	o_ns_yellow : BUFFER STD_LOGIC
	);
END COMPONENT;
BEGIN
	i1 : TrafficLight
	PORT MAP (
-- list connections between master ports and signals
	i_sys_clk => i_sys_clk,
	i_sys_emergency => i_sys_emergency,
	i_sys_rst => i_sys_rst,
	o_ew_green => o_ew_green,
	o_ew_red => o_ew_red,
	o_ew_tens_a => o_ew_tens_a,
	o_ew_tens_b => o_ew_tens_b,
	o_ew_tens_c => o_ew_tens_c,
	o_ew_tens_d => o_ew_tens_d,
	o_ew_tens_e => o_ew_tens_e,
	o_ew_tens_f => o_ew_tens_f,
	o_ew_tens_g => o_ew_tens_g,
	o_ew_units_a => o_ew_units_a,
	o_ew_units_b => o_ew_units_b,
	o_ew_units_c => o_ew_units_c,
	o_ew_units_d => o_ew_units_d,
	o_ew_units_e => o_ew_units_e,
	o_ew_units_f => o_ew_units_f,
	o_ew_units_g => o_ew_units_g,
	o_ew_yellow => o_ew_yellow,
	o_ns_green => o_ns_green,
	o_ns_red => o_ns_red,
	o_ns_tens_a => o_ns_tens_a,
	o_ns_tens_b => o_ns_tens_b,
	o_ns_tens_c => o_ns_tens_c,
	o_ns_tens_d => o_ns_tens_d,
	o_ns_tens_e => o_ns_tens_e,
	o_ns_tens_f => o_ns_tens_f,
	o_ns_tens_g => o_ns_tens_g,
	o_ns_units_a => o_ns_units_a,
	o_ns_units_b => o_ns_units_b,
	o_ns_units_c => o_ns_units_c,
	o_ns_units_d => o_ns_units_d,
	o_ns_units_e => o_ns_units_e,
	o_ns_units_f => o_ns_units_f,
	o_ns_units_g => o_ns_units_g,
	o_ns_yellow => o_ns_yellow
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END TrafficLight_arch;
